In-chip dynamic current distribution simulation technology for power device layout design


In-chip current distribution verification technology for power devices that takes into account the effect of layout noise.

Abstract:

“This paper presents an in-chip current distribution verification technology for power devices that takes into account the effect of implantation noise. The proposed method makes it possible to verify the dynamic distribution of the current in a chip taking into account the influence of layout parasites from the initial stage of the development of the device by reworking each element of the TCAD technology, the Spice model and of layout parasite extraction technology for power devices and linking them seamlessly. We report that this method was applied to the layout optimization of our 8th generation IGBTs, and that the current variation in the chip could be reduced by about 50% compared to the layout structure. conventional. “

Find the technical document link here.

T. Saito et al., “Dynamic in-chip current distribution simulation technology for power device layout design”, 2021 33rd International Symposium on Power Semiconductor Devices and Circuits (ISPSD), 2021, pp. 159-162, doi: 10.23919 / ISPSD50666 .2021.9452233.


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